System by which a sense amplifier is connected to a bit line pair in DRAM, which is a type of semiconductor storage device, include an open bit line system and a folded bit line system (see Japanese Laid-Open Patent Application No. 2003-273245). In an open bit line system, two bit lines that are connected to a single sense amplifier are wired in opposite directions from each other on either side of the sense amplifier. In a folded bit line system, two bit lines that are connected to a single sense amplifier are turned back at the sense amplifier and wired in the same direction.
FIG. 6 is a circuit diagram showing the basic structure of a folded bit line system.
As shown in FIG. 6, in the folded bit line system, the pair of bit lines BL, /BL connected to the sense amplifier SA is laid parallel and in the same direction. Both bit lines BL, /BL are therefore intersected by the same word line WL. Accordingly, in order for a single bit of data to be stored in a single memory cell MC, a memory cell MC must be placed at the intersection point of any one of the bit lines BL, /BL with a word line WL and a memory cell MC cannot be placed at all the nodes.
FIG. 7 is a circuit diagram showing the basic structure of the open bit line system.
As shown in FIG. 7, in the open bit line system, the two of bit lines BL, /BL connected to the sense amplifier SA are laid in opposite directions from each other on either side of the sense amplifier. Therefore, the same word line WL never intersects both of the bit lines BL, /BL. It is therefore possible to place a memory cell MC at all of the nodes. In this case, the theoretical minimum surface area of a memory cell is 4F2 (2F×2F), according to a system in which the surface area of a memory cell is indicated using a value (minimum feature size) “F” that is half the pitch of the word lines, and the typical surface area of a memory cell at a single node is 6F2 (2F×3F).
In a conventional DRAM that uses an open bit line system, sense amplifiers SA are in a distributed arrangement, and the density with which memory cells are formed in the memory mats 101A, 101C at the end portions within the chip, or at the end portions (portions in which the continuity of the memory mats is interrupted) of the peripheral circuit, is half the density with which memory cells are formed in the other memory mat 101B, as shown in FIG. 8. When such a difference in density exists, the optimal processing conditions differ between memory mats. In order to eliminate this type of density difference, dummy bit lines DBL that are not connected to the sense amplifier SA must be wired to the memory mats 101A, 101C, and dummy cells DC must be formed at the intersections of the dummy bit lines DBL with the word lines, as shown in FIG. 9. This configuration makes it possible to make the optimal processing conditions nearly the same among the memory mats 101A, 101C at the ends and the memory mat 101B in the middle.
However, this type of dummy cell DC is not utilized at all in the conventional DRAM, and was of no use to the circuit.